1. Technical Field
This disclosure relates to non-volatile memory cells that may be programmed in the last fabrication stages of a circuit, and more specifically to a secure non-volatile memory, i.e., a memory whose content is difficult to reconstruct by analysis of the final circuit.
2. Description of the Related Art
Many circuits may embed firmware in a non-volatile memory. In most applications, the non-volatile memory is ROM. A drawback of a ROM is that its content is relatively easy to reconstruct by structural analysis of the circuit, which makes it less adapted to cryptography applications.
FIG. 1 schematically shows a non-volatile memory cell, such as disclosed in U.S. Pat. No. 7,697,319, whose content is rendered difficult to reconstruct by conventional analysis means. The basis of the cell is an RS-type bistable flip-flop comprised, for instance, of two NOR gates 10, 11. The output Q of each gate is connected to a first input of the other gate. The second inputs of gates 10, 11 receive a same reset signal RST, which is uncommon for an RS flip-flop, which should normally receive complementary states on these inputs for setting the state of the flip-flop.
During normal operation, signal RST is low, whereby gates 10, 11 behave as cross-coupled inverters. They provide complementary states a their outputs Q0, Q1. Hence, each gate confirms the state of the other gate. The state stored in the cell is taken from one of the outputs Q, say Q0.
When signal RST goes high, the outputs of gates 10, 11 are both forced to 0, which normally corresponds to a “prohibited” state. Indeed, when signal RST goes low again, the flip-flop is in a metastable state; gates 10, 11 both tend to go high—the first one to get there prevents the other from going high. When both gates are identical, it is not possible to foresee which one will go high. This uncertainty is encountered upon power-on of the circuit including the flip-flop.
The above mentioned patent provides making gates 10, 11 unbalanced in order to promote switching of the cell to a foreseeable state when it goes through a metastable state, upon power-on or after a reset.
FIG. 2 will be used to illustrate how that is done. It shows the structure of a NOR gate. The gate comprises two P-MOS transistors MP1, MP2, connected in series to a high power supply rail Vdd. Two N-MOS transistors MN1, MN2, are connected in parallel and connect transistors MP1, MP2 to a low power supply rail Vss.
The connection node between the sources of transistors MP2, MN1 and MN2 forms the output Q of the NOR gate. The gates of transistors MP1 and MN1 are connected together and form the first input A of the NOR gate. The second input B of the NOR gate is formed by the gates of transistors MP2 and MN2.
In order to unbalance the shown NOR gate with respect to the other NOR gate (not shown) of the flip-flop, without changing its physical structure, the threshold voltage of the N (or P) transistors of the gate is modified by changing the channel doping (or drain and source doping) by ion implant. When, for instance, the threshold voltage of the P transistors is thus increased, these transistors cease to conduct, thus cease to pull the output high, earlier than the P transistors of the other NOR gate. Therefore, the other NOR gate systematically “wins” in going high when the flip-flop is in a metastable state. A non-volatile “1” or “0” can thus be programmed in the cell by choosing one or the other NOR gate for the ion implant. Such programming may be achieved through a mask in the last fabrication steps of the circuit.
Such a memory cell has the same physical structure, whether it is programmed to 1 or to 0. It is thus generally not possible to find its programmed state through structural analysis means. Other analysis techniques however exist that may allow, in a circuit in operation, to detect the state stored in such a cell.